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* pdm: Try switch to 2 stage CICJon Nordby2025-08-08
* pdm: Try more HPF fixesJon Nordby2025-08-08
* pdm: Try add high pass filter for DC blocking/removalJon Nordby2025-08-08
* pdm: Make the sinewave test actually assert relevant valuesJon Nordby2025-08-08
* pdm: Fix python path for testsJon Nordby2025-08-08
* README: Notes on TinytapeoutJon Nordby2025-07-20
* filter: transmit 16000 Hz signed 8 bit PCM over UARTMartin Stensgård2025-07-16
* move top -> recordMartin Stensgård2025-07-16
* Makefile: add gui by nextpnrMartin Stensgård2025-07-16
* bindings: clang-formatMartin Stensgård2025-05-14
* bindings/README: add python dependenciesMartin Stensgård2025-05-14
* Track runtime of PDM conversionJon Nordby2025-05-14
* cic3_pdm: Silence a warning from VerilatorJon Nordby2025-05-14
* bindings: Improve test for PDM to PCMJon Nordby2025-05-14
* bindings: Actually build cic3_pdm codeJon Nordby2025-05-14
* bindings: Add a unified MakefileJon Nordby2025-05-14
* LICENSE: ISCMartin Stensgård2025-05-02
* bindings/README: give debian command for installing python dependenciesMartin Stensgård2025-05-02
* bindings: Use verilator_lib in PythonJon Nordby2025-05-02
* bindings: Example of using pybind11 with numpyJon Nordby2025-05-02
* Remove unused pdm_outJon Nordby2025-05-02
* cocotb: Have two tests, share coreJon Nordby2025-05-02
* cocotb: Specify some argumentsJon Nordby2025-05-02
* cocotb: Test and fix 1khz sineJon Nordby2025-05-02
* verilator_lib: wrap verilog module in c++ library in c++ executableMartin Stensgård2025-05-02
* verilator_mul: multiply 32 bit integers, 38 MHz on puMartin Stensgård2025-05-02
* verilator_add: benchmark 8-bit addition: 37 MHz on puMartin Stensgård2025-05-02
* verilator_example_tracing/.gitignore: +/dump.vcdMartin Stensgård2025-04-27
* verilator_example_tracing: dump value changeMartin Stensgård2025-04-27
* cocotb: Run multiple PCM samplesJon Nordby2025-04-26
* cocotb: Try to test a CIC filterJon Nordby2025-04-26
* cocotb: Switch to plain Verilog, from SystemVerilogJon Nordby2025-04-26
* cocotb: Try to run quickstartJon Nordby2025-04-26
* pdm2pcm: Default to 4 stagesJon Nordby2025-04-26
* pdm2pcm: CIC filter that worksJon Nordby2025-04-26
* pdm2pcm: Try add support for CICJon Nordby2025-04-26
* verilator_example_systemc: helloMartin Stensgård2025-04-26
* .gitignore: +coreMartin Stensgård2025-04-26
* verilator_example_c++: helloMartin Stensgård2025-04-26
* .clang-format: Language Cpp; BasedOnStyle LLVMMartin Stensgård2025-04-26
* verilator_example_binary/Makefile: delete unused TOPMartin Stensgård2025-04-26
* verilator_example_binary: helloMartin Stensgård2025-04-26
* README: reference verilatorMartin Stensgård2025-04-26
* README: CIC 1337Martin Stensgård2025-04-26
* README: reference p. trujilo's rms in fpgaMartin Stensgård2025-04-18
* README: reference ericgineer's cic filter in verilogMartin Stensgård2025-04-18
* tools: Unhardcode parametersJon Nordby2025-04-18
* tools: Fixup PDM reference conversionJon Nordby2025-04-18
* tools: Simplify test signal to 1 khz sineJon Nordby2025-04-18
* tools: WIP on PDM<->PCM conversion in PythonJon Nordby2025-04-18
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