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| author | Jon Nordby <jononor@gmail.com> | 2025-04-26 18:09:02 +0200 |
|---|---|---|
| committer | Jon Nordby <jononor@gmail.com> | 2025-04-26 21:33:29 +0200 |
| commit | b2b664b2596b48048ba97c5b43f3f29345c6bdb3 (patch) | |
| tree | 55c85518cc8d920546e081fa9e4a6f6c3ada6909 | |
| parent | ea5c8903b101708b49c2789ebc7d6e5f9453f119 (diff) | |
cocotb: Switch to plain Verilog, from SystemVerilog
| -rw-r--r-- | cocotb_try/Makefile | 2 | ||||
| -rw-r--r-- | cocotb_try/my_design.v (renamed from cocotb_try/my_design.sv) | 0 |
2 files changed, 1 insertions, 1 deletions
diff --git a/cocotb_try/Makefile b/cocotb_try/Makefile index 2648771..2d4fe2b 100644 --- a/cocotb_try/Makefile +++ b/cocotb_try/Makefile @@ -4,7 +4,7 @@ SIM ?= verilator TOPLEVEL_LANG ?= verilog -VERILOG_SOURCES += $(PWD)/my_design.sv +VERILOG_SOURCES += $(PWD)/my_design.v # use VHDL_SOURCES for VHDL files # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file diff --git a/cocotb_try/my_design.sv b/cocotb_try/my_design.v index 458ac8e..458ac8e 100644 --- a/cocotb_try/my_design.sv +++ b/cocotb_try/my_design.v |