From b2b664b2596b48048ba97c5b43f3f29345c6bdb3 Mon Sep 17 00:00:00 2001
From: Jon Nordby <jononor@gmail.com>
Date: Sat, 26 Apr 2025 18:09:02 +0200
Subject: cocotb: Switch to plain Verilog, from SystemVerilog

---
 cocotb_try/Makefile     |  2 +-
 cocotb_try/my_design.sv | 15 ---------------
 cocotb_try/my_design.v  | 15 +++++++++++++++
 3 files changed, 16 insertions(+), 16 deletions(-)
 delete mode 100644 cocotb_try/my_design.sv
 create mode 100644 cocotb_try/my_design.v

diff --git a/cocotb_try/Makefile b/cocotb_try/Makefile
index 2648771..2d4fe2b 100644
--- a/cocotb_try/Makefile
+++ b/cocotb_try/Makefile
@@ -4,7 +4,7 @@
 SIM ?= verilator
 TOPLEVEL_LANG ?= verilog
 
-VERILOG_SOURCES += $(PWD)/my_design.sv
+VERILOG_SOURCES += $(PWD)/my_design.v
 # use VHDL_SOURCES for VHDL files
 
 # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
diff --git a/cocotb_try/my_design.sv b/cocotb_try/my_design.sv
deleted file mode 100644
index 458ac8e..0000000
--- a/cocotb_try/my_design.sv
+++ /dev/null
@@ -1,15 +0,0 @@
-// This file is public domain, it can be freely copied without restrictions.
-// SPDX-License-Identifier: CC0-1.0
-
-module my_design(input logic clk);
-
-  timeunit 1ns;
-  timeprecision 1ns;
-
-  logic my_signal_1;
-  logic my_signal_2;
-
-  assign my_signal_1 = 1'bx;
-  assign my_signal_2 = 0;
-
-endmodule
diff --git a/cocotb_try/my_design.v b/cocotb_try/my_design.v
new file mode 100644
index 0000000..458ac8e
--- /dev/null
+++ b/cocotb_try/my_design.v
@@ -0,0 +1,15 @@
+// This file is public domain, it can be freely copied without restrictions.
+// SPDX-License-Identifier: CC0-1.0
+
+module my_design(input logic clk);
+
+  timeunit 1ns;
+  timeprecision 1ns;
+
+  logic my_signal_1;
+  logic my_signal_2;
+
+  assign my_signal_1 = 1'bx;
+  assign my_signal_2 = 0;
+
+endmodule
-- 
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