diff options
Diffstat (limited to 'cocotb_try/Makefile')
| -rw-r--r-- | cocotb_try/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cocotb_try/Makefile b/cocotb_try/Makefile index 2648771..2d4fe2b 100644 --- a/cocotb_try/Makefile +++ b/cocotb_try/Makefile @@ -4,7 +4,7 @@ SIM ?= verilator TOPLEVEL_LANG ?= verilog -VERILOG_SOURCES += $(PWD)/my_design.sv +VERILOG_SOURCES += $(PWD)/my_design.v # use VHDL_SOURCES for VHDL files # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file |