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| author | Martin Stensgård <mastensg@mastensg.net> | 2025-04-26 17:10:37 +0200 |
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| committer | Martin Stensgård <mastensg@mastensg.net> | 2025-04-26 17:10:37 +0200 |
| commit | 1cb35c28b523d3849385dbeca5369511bb9a0b58 (patch) | |
| tree | 4b220ae0e7202b903e6e23b8d74ecf5917bb4196 | |
| parent | 0aa8e261d2fbb075ff253f72bea39f830293c4e1 (diff) | |
README: reference verilator
| -rw-r--r-- | README | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -29,5 +29,8 @@ References https://tomverbeure.github.io/2020/12/20/Design-of-a-Multi-Stage-PDM-to-PCM-Decimation-Pipeline.html RMS in FPGA https://www.controlpaths.com/2022/07/18/true-rms-compute-in-fpga/ + Verilator + https://www.veripool.org/verilator/ + https://verilator.org/guide/latest/ Verilog by Example (Blaine C. Raedler 2021) http://readler.com/books2.html |