From 1cb35c28b523d3849385dbeca5369511bb9a0b58 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Stensg=C3=A5rd?= Date: Sat, 26 Apr 2025 17:10:37 +0200 Subject: README: reference verilator --- README | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README b/README index 4d429aa..91d8167 100644 --- a/README +++ b/README @@ -29,5 +29,8 @@ References https://tomverbeure.github.io/2020/12/20/Design-of-a-Multi-Stage-PDM-to-PCM-Decimation-Pipeline.html RMS in FPGA https://www.controlpaths.com/2022/07/18/true-rms-compute-in-fpga/ + Verilator + https://www.veripool.org/verilator/ + https://verilator.org/guide/latest/ Verilog by Example (Blaine C. Raedler 2021) http://readler.com/books2.html -- cgit v1.2.3