verilator_mul: multiply 32 bit integers, 38 MHz on pu

4 files changed, 59 insertions, 0 deletions

diff --git a/verilator_mul/.gitignore b/verilator_mul/.gitignore
new file mode 100644
index 0000000..d38e9f1
--- /dev/null
+++ b/verilator_mul/.gitignore
@@ -0,0 +1 @@
+/obj_dir
diff --git a/verilator_mul/Makefile b/verilator_mul/Makefile
new file mode 100644
index 0000000..d98a603
--- /dev/null
+++ b/verilator_mul/Makefile
@@ -0,0 +1,12 @@
+all: obj_dir/Vmul
+
+check: all
+	obj_dir/Vmul
+
+clean:
+	rm -fr obj_dir
+
+.PHONY: all check clean
+
+obj_dir/Vmul: mul.v sim_main.cc
+	verilator --cc --exe --build -j 0 -Wall sim_main.cc mul.v
diff --git a/verilator_mul/mul.v b/verilator_mul/mul.v
new file mode 100644
index 0000000..67fb36b
--- /dev/null
+++ b/verilator_mul/mul.v
@@ -0,0 +1,10 @@
+module mul(
+	input			clk,
+	input		[31:0]	x,
+	input		[31:0]	y,
+	output	reg	[31:0]	p
+);
+	always @(posedge clk) begin
+		p <= x * y;
+	end
+endmodule
diff --git a/verilator_mul/sim_main.cc b/verilator_mul/sim_main.cc
new file mode 100644
index 0000000..b525e00
--- /dev/null
+++ b/verilator_mul/sim_main.cc
@@ -0,0 +1,36 @@
+#include <cstdint>
+#include <cstdio>
+
+#include "Vmul.h"
+#include "verilated.h"
+
+enum { MAX = 10000 };
+
+int
+main(int argc, char **argv)
+{
+	VerilatedContext *cp = new VerilatedContext;
+	cp->commandArgs(argc, argv);
+
+	Vmul *top = new Vmul{cp};
+	top->clk = 0;
+
+	int numclks = 0;
+	for (int x = 0; x < MAX; ++x) {
+		for (int y = 0; y < MAX; ++y) {
+			top->x = x;
+			top->y = y;
+			top->clk = 1;
+			top->eval();
+
+			int p = top->p;
+			if (p != (uint32_t)(x * y))
+				printf("%4d * %4d = %4d\n", x, y, p);
+
+			top->clk = 0;
+			top->eval();
+			++numclks;
+		}
+	}
+	fprintf(stderr, "%d clock cycles\n", numclks);
+}