verilator_mul: multiply 32 bit integers, 38 MHz on pu

1 files changed, 10 insertions, 0 deletions

diff --git a/verilator_mul/mul.v b/verilator_mul/mul.v
new file mode 100644
index 0000000..67fb36b
--- /dev/null
+++ b/verilator_mul/mul.v
@@ -0,0 +1,10 @@
+module mul(
+	input			clk,
+	input		[31:0]	x,
+	input		[31:0]	y,
+	output	reg	[31:0]	p
+);
+	always @(posedge clk) begin
+		p <= x * y;
+	end
+endmodule