From 0e422ec41b33216b12d8a98612d1b4b3cd84b3a7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Stensg=C3=A5rd?= <mastensg@mastensg.net>
Date: Fri, 2 May 2025 20:09:27 +0200
Subject: verilator_mul: multiply 32 bit integers, 38 MHz on pu

---
 verilator_mul/mul.v | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 verilator_mul/mul.v

(limited to 'verilator_mul/mul.v')

diff --git a/verilator_mul/mul.v b/verilator_mul/mul.v
new file mode 100644
index 0000000..67fb36b
--- /dev/null
+++ b/verilator_mul/mul.v
@@ -0,0 +1,10 @@
+module mul(
+	input			clk,
+	input		[31:0]	x,
+	input		[31:0]	y,
+	output	reg	[31:0]	p
+);
+	always @(posedge clk) begin
+		p <= x * y;
+	end
+endmodule
-- 
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