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authorMartin Stensgård <mastensg@mastensg.net>2025-05-02 20:52:27 +0200
committerMartin Stensgård <mastensg@mastensg.net>2025-05-02 20:52:27 +0200
commitcb019a43f55e08aa4c12573270a32213c823e1cb (patch)
tree7bb17c0dde760db6493894e17c19befe5cb5c3e2 /verilator_lib/Makefile
parent0e422ec41b33216b12d8a98612d1b4b3cd84b3a7 (diff)
verilator_lib: wrap verilog module in c++ library in c++ executable
Diffstat (limited to 'verilator_lib/Makefile')
-rw-r--r--verilator_lib/Makefile15
1 files changed, 15 insertions, 0 deletions
diff --git a/verilator_lib/Makefile b/verilator_lib/Makefile
new file mode 100644
index 0000000..3ea76fe
--- /dev/null
+++ b/verilator_lib/Makefile
@@ -0,0 +1,15 @@
+all: wrap
+
+check: all
+ ./wrap
+
+clean:
+ rm -fr obj_dir
+
+.PHONY: all check clean
+
+obj_dir/libsim.so: mul.v sim.cc
+ verilator --cc --lib-create sim --build -j 0 -Wall mul.v sim.cc
+
+wrap: obj_dir/libsim.so
+ g++ -Iobj_dir -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -o wrap wrap.cc obj_dir/libsim.so