diff options
author | Martin Stensgård <mastensg@mastensg.net> | 2025-05-02 20:52:27 +0200 |
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committer | Martin Stensgård <mastensg@mastensg.net> | 2025-05-02 20:52:27 +0200 |
commit | cb019a43f55e08aa4c12573270a32213c823e1cb (patch) | |
tree | 7bb17c0dde760db6493894e17c19befe5cb5c3e2 /verilator_lib | |
parent | 0e422ec41b33216b12d8a98612d1b4b3cd84b3a7 (diff) |
verilator_lib: wrap verilog module in c++ library in c++ executable
Diffstat (limited to 'verilator_lib')
-rw-r--r-- | verilator_lib/.gitignore | 2 | ||||
-rw-r--r-- | verilator_lib/Makefile | 15 | ||||
-rw-r--r-- | verilator_lib/mul.v | 10 | ||||
-rw-r--r-- | verilator_lib/sim.cc | 36 | ||||
-rw-r--r-- | verilator_lib/wrap.cc | 10 |
5 files changed, 73 insertions, 0 deletions
diff --git a/verilator_lib/.gitignore b/verilator_lib/.gitignore new file mode 100644 index 0000000..27f7104 --- /dev/null +++ b/verilator_lib/.gitignore @@ -0,0 +1,2 @@ +/obj_dir +/wrap diff --git a/verilator_lib/Makefile b/verilator_lib/Makefile new file mode 100644 index 0000000..3ea76fe --- /dev/null +++ b/verilator_lib/Makefile @@ -0,0 +1,15 @@ +all: wrap + +check: all + ./wrap + +clean: + rm -fr obj_dir + +.PHONY: all check clean + +obj_dir/libsim.so: mul.v sim.cc + verilator --cc --lib-create sim --build -j 0 -Wall mul.v sim.cc + +wrap: obj_dir/libsim.so + g++ -Iobj_dir -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -o wrap wrap.cc obj_dir/libsim.so diff --git a/verilator_lib/mul.v b/verilator_lib/mul.v new file mode 100644 index 0000000..67fb36b --- /dev/null +++ b/verilator_lib/mul.v @@ -0,0 +1,10 @@ +module mul( + input clk, + input [31:0] x, + input [31:0] y, + output reg [31:0] p +); + always @(posedge clk) begin + p <= x * y; + end +endmodule diff --git a/verilator_lib/sim.cc b/verilator_lib/sim.cc new file mode 100644 index 0000000..3ca8f67 --- /dev/null +++ b/verilator_lib/sim.cc @@ -0,0 +1,36 @@ +#include <cstdint> +#include <cstdio> + +#include "Vmul.h" +#include "verilated.h" + +enum { MAX = 10000 }; + +int +sim(void) +{ + VerilatedContext *cp = new VerilatedContext; + + Vmul *top = new Vmul{cp}; + top->clk = 0; + + int numclks = 0; + for (int x = 0; x < MAX; ++x) { + for (int y = 0; y < MAX; ++y) { + top->x = x; + top->y = y; + top->clk = 1; + top->eval(); + + int p = top->p; + if (p != (uint32_t)(x * y)) + printf("%4d * %4d = %4d\n", x, y, p); + + top->clk = 0; + top->eval(); + ++numclks; + } + } + fprintf(stderr, "%d clock cycles\n", numclks); + return 0; +} diff --git a/verilator_lib/wrap.cc b/verilator_lib/wrap.cc new file mode 100644 index 0000000..8d14fbd --- /dev/null +++ b/verilator_lib/wrap.cc @@ -0,0 +1,10 @@ +#include <cstdio> + +int sim(void); + +int +main() +{ + fprintf(stderr, "nå kaller jeg sim...\n"); + sim(); +} |