cocotb: Switch to plain Verilog, from SystemVerilog

1 files changed, 15 insertions, 0 deletions

diff --git a/cocotb_try/my_design.v b/cocotb_try/my_design.v
new file mode 100644
index 0000000..458ac8e
--- /dev/null
+++ b/cocotb_try/my_design.v
@@ -0,0 +1,15 @@
+// This file is public domain, it can be freely copied without restrictions.
+// SPDX-License-Identifier: CC0-1.0
+
+module my_design(input logic clk);
+
+  timeunit 1ns;
+  timeprecision 1ns;
+
+  logic my_signal_1;
+  logic my_signal_2;
+
+  assign my_signal_1 = 1'bx;
+  assign my_signal_2 = 0;
+
+endmodule