From b2b664b2596b48048ba97c5b43f3f29345c6bdb3 Mon Sep 17 00:00:00 2001
From: Jon Nordby <jononor@gmail.com>
Date: Sat, 26 Apr 2025 18:09:02 +0200
Subject: cocotb: Switch to plain Verilog, from SystemVerilog

---
 cocotb_try/my_design.v | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 cocotb_try/my_design.v

(limited to 'cocotb_try/my_design.v')

diff --git a/cocotb_try/my_design.v b/cocotb_try/my_design.v
new file mode 100644
index 0000000..458ac8e
--- /dev/null
+++ b/cocotb_try/my_design.v
@@ -0,0 +1,15 @@
+// This file is public domain, it can be freely copied without restrictions.
+// SPDX-License-Identifier: CC0-1.0
+
+module my_design(input logic clk);
+
+  timeunit 1ns;
+  timeprecision 1ns;
+
+  logic my_signal_1;
+  logic my_signal_2;
+
+  assign my_signal_1 = 1'bx;
+  assign my_signal_2 = 0;
+
+endmodule
-- 
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