cocotb: Switch to plain Verilog, from SystemVerilog

1 files changed, 0 insertions, 15 deletions

diff --git a/cocotb_try/my_design.sv b/cocotb_try/my_design.sv
deleted file mode 100644
index 458ac8e..0000000
--- a/cocotb_try/my_design.sv
+++ /dev/null
@@ -1,15 +0,0 @@
-// This file is public domain, it can be freely copied without restrictions.
-// SPDX-License-Identifier: CC0-1.0
-
-module my_design(input logic clk);
-
-  timeunit 1ns;
-  timeprecision 1ns;
-
-  logic my_signal_1;
-  logic my_signal_2;
-
-  assign my_signal_1 = 1'bx;
-  assign my_signal_2 = 0;
-
-endmodule