From b2b664b2596b48048ba97c5b43f3f29345c6bdb3 Mon Sep 17 00:00:00 2001 From: Jon Nordby Date: Sat, 26 Apr 2025 18:09:02 +0200 Subject: cocotb: Switch to plain Verilog, from SystemVerilog --- cocotb_try/my_design.sv | 15 --------------- 1 file changed, 15 deletions(-) delete mode 100644 cocotb_try/my_design.sv (limited to 'cocotb_try/my_design.sv') diff --git a/cocotb_try/my_design.sv b/cocotb_try/my_design.sv deleted file mode 100644 index 458ac8e..0000000 --- a/cocotb_try/my_design.sv +++ /dev/null @@ -1,15 +0,0 @@ -// This file is public domain, it can be freely copied without restrictions. -// SPDX-License-Identifier: CC0-1.0 - -module my_design(input logic clk); - - timeunit 1ns; - timeprecision 1ns; - - logic my_signal_1; - logic my_signal_2; - - assign my_signal_1 = 1'bx; - assign my_signal_2 = 0; - -endmodule -- cgit v1.2.3