diff options
author | Martin Stensgård <mastensg@mastensg.net> | 2025-05-02 19:55:31 +0200 |
---|---|---|
committer | Martin Stensgård <mastensg@mastensg.net> | 2025-05-02 19:55:31 +0200 |
commit | f38b4c8370f293ddb19f623e3112cf28bc0088b6 (patch) | |
tree | 7a75d7cb4d061c636a1cd1e4eaaea9919c78a358 /verilator_add/sim_main.cc | |
parent | 4472067cda484a5abad18ace2696689fdd718956 (diff) |
verilator_add: benchmark 8-bit addition: 37 MHz on pu
Diffstat (limited to 'verilator_add/sim_main.cc')
-rw-r--r-- | verilator_add/sim_main.cc | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/verilator_add/sim_main.cc b/verilator_add/sim_main.cc new file mode 100644 index 0000000..6059d63 --- /dev/null +++ b/verilator_add/sim_main.cc @@ -0,0 +1,36 @@ +#include <cstdint> +#include <cstdio> + +#include "Vadd.h" +#include "verilated.h" + +enum { MAX = 10000 }; + +int +main(int argc, char **argv) +{ + VerilatedContext *cp = new VerilatedContext; + cp->commandArgs(argc, argv); + + Vadd *top = new Vadd{cp}; + top->clk = 0; + + int numclks = 0; + for (int x = 0; x < MAX; ++x) { + for (int y = 0; y < MAX; ++y) { + top->x = x; + top->y = y; + top->clk = 1; + top->eval(); + + int s = top->s; + if (s != (uint8_t)(x + y)) + printf("%4d + %4d = %4d\n", x, y, s); + + top->clk = 0; + top->eval(); + ++numclks; + } + } + fprintf(stderr, "%d clock cycles\n", numclks); +} |