From f38b4c8370f293ddb19f623e3112cf28bc0088b6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Stensg=C3=A5rd?= Date: Fri, 2 May 2025 19:55:31 +0200 Subject: verilator_add: benchmark 8-bit addition: 37 MHz on pu --- verilator_add/sim_main.cc | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 verilator_add/sim_main.cc (limited to 'verilator_add/sim_main.cc') diff --git a/verilator_add/sim_main.cc b/verilator_add/sim_main.cc new file mode 100644 index 0000000..6059d63 --- /dev/null +++ b/verilator_add/sim_main.cc @@ -0,0 +1,36 @@ +#include +#include + +#include "Vadd.h" +#include "verilated.h" + +enum { MAX = 10000 }; + +int +main(int argc, char **argv) +{ + VerilatedContext *cp = new VerilatedContext; + cp->commandArgs(argc, argv); + + Vadd *top = new Vadd{cp}; + top->clk = 0; + + int numclks = 0; + for (int x = 0; x < MAX; ++x) { + for (int y = 0; y < MAX; ++y) { + top->x = x; + top->y = y; + top->clk = 1; + top->eval(); + + int s = top->s; + if (s != (uint8_t)(x + y)) + printf("%4d + %4d = %4d\n", x, y, s); + + top->clk = 0; + top->eval(); + ++numclks; + } + } + fprintf(stderr, "%d clock cycles\n", numclks); +} -- cgit v1.2.3