verilator_add: benchmark 8-bit addition: 37 MHz on pu

1 files changed, 10 insertions, 0 deletions

diff --git a/verilator_add/add.v b/verilator_add/add.v
new file mode 100644
index 0000000..240c97e
--- /dev/null
+++ b/verilator_add/add.v
@@ -0,0 +1,10 @@
+module add(
+	input			clk,
+	input		[7:0]	x,
+	input		[7:0]	y,
+	output	reg	[7:0]	s
+);
+	always @(posedge clk) begin
+		s <= x + y;
+	end
+endmodule