From f38b4c8370f293ddb19f623e3112cf28bc0088b6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Stensg=C3=A5rd?= <mastensg@mastensg.net>
Date: Fri, 2 May 2025 19:55:31 +0200
Subject: verilator_add: benchmark 8-bit addition: 37 MHz on pu

---
 verilator_add/add.v | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 verilator_add/add.v

(limited to 'verilator_add/add.v')

diff --git a/verilator_add/add.v b/verilator_add/add.v
new file mode 100644
index 0000000..240c97e
--- /dev/null
+++ b/verilator_add/add.v
@@ -0,0 +1,10 @@
+module add(
+	input			clk,
+	input		[7:0]	x,
+	input		[7:0]	y,
+	output	reg	[7:0]	s
+);
+	always @(posedge clk) begin
+		s <= x + y;
+	end
+endmodule
-- 
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