5 files changed, 71 insertions, 0 deletions
diff --git a/example/Makefile b/example/Makefile
new file mode 100644
index 0000000..a55ea4c
--- /dev/null
+++ b/example/Makefile
@@ -0,0 +1,11 @@
+
+rot.bin: rot.v rot.pcf
+	yosys -q -p "synth_ice40 -blif rot.blif" rot.v
+	arachne-pnr -p rot.pcf rot.blif -o rot.txt
+	icebox_explain rot.txt > rot.ex
+	icepack rot.txt rot.bin
+	./ice4pi_prog rot.bin
+#	iceprog rot.bin
+
+clean:
+	rm -f rot.blif rot.txt rot.ex rot.bin
diff --git a/example/README b/example/README
new file mode 100644
index 0000000..ddc381d
--- /dev/null
+++ b/example/README
@@ -0,0 +1,13 @@
+To install all necessary packages and synthesize and program ice4pi:
+
+ sudo apt-get install yosys fpga-icestorm arachne-pnr
+ make
+
+1. Make sure your Pi has SPI enabled
+
+2. There is a problem in arachne-pnr reporting bogus dependency conflict that can be worked around:
+
+ apt-get source arachne-pnr
+ cd arachne-pnr-0.1+20180909git840bdfd-1.1/
+ dpkg-buildpackage -us -uc -j2
+ sudo dpkg -i ../arachne*.deb
diff --git a/example/ice4pi_prog b/example/ice4pi_prog
new file mode 100755
index 0000000..dea5c7a
--- /dev/null
+++ b/example/ice4pi_prog
@@ -0,0 +1,7 @@
+#!/bin/bash
+echo 24 > /sys/class/gpio/export
+echo out > /sys/class/gpio/gpio24/direction
+tr '\0' '\377' < /dev/zero | dd bs=1M count=4 of=image iflag=fullblock
+dd if=${1} conv=notrunc of=image
+flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=20000 -w image
+echo in > /sys/class/gpio/gpio24/direction
diff --git a/example/rot.pcf b/example/rot.pcf
new file mode 100644
index 0000000..46b013f
--- /dev/null
+++ b/example/rot.pcf
@@ -0,0 +1,8 @@
+# For the iCE40HX-1K iCEstick
+
+set_io D1 99
+set_io D2 98
+set_io D3 97
+set_io D4 96
+set_io D5 95
+set_io clk 21
diff --git a/example/rot.v b/example/rot.v
new file mode 100644
index 0000000..e7bc2a1
--- /dev/null
+++ b/example/rot.v
@@ -0,0 +1,32 @@
+
+module top(input clk, output D1, output D2, output D3, output D4, output D5);
+   
+   reg ready = 0;
+   reg [23:0]     divider;
+   reg [3:0]      rot;
+   
+   always @(posedge clk) begin
+      if (ready) 
+        begin
+           if (divider == 12000000) 
+             begin
+                divider <= 0;
+                rot <= {rot[2:0], rot[3]};
+             end
+           else 
+             divider <= divider + 1;
+        end
+      else 
+        begin
+           ready <= 1;
+           rot <= 4'b1110;
+           divider <= 0;
+        end
+   end
+   
+   assign D1 = rot[0];
+   assign D2 = rot[1];
+   assign D3 = rot[2];
+   assign D4 = rot[3];
+   assign D5 = 1;
+endmodule // top