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# Makefile
# defaults
SIM ?= verilator
TOPLEVEL_LANG ?= verilog
VERILOG_SOURCES += $(PWD)/cic3_pdm.v
# use VHDL_SOURCES for VHDL files
# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
TOPLEVEL = cic3_pdm
# MODULE is the basename of the Python test file
MODULE = test_cic
# Try to make simlation faster
#WAVES=0
#COCOTB_HDL_TIMEPRECISION=100ps
VERILATOR_FLAGS = -O3 --no-debug --output-split 20000
# include cocotb's make rules to take care of the simulator setup
include $(shell cocotb-config --makefiles)/Makefile.sim
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