1 files changed, 18 insertions, 0 deletions
diff --git a/cocotb_try/Makefile b/cocotb_try/Makefile
new file mode 100644
index 0000000..2648771
--- /dev/null
+++ b/cocotb_try/Makefile
@@ -0,0 +1,18 @@
+# Makefile
+
+# defaults
+SIM ?= verilator
+TOPLEVEL_LANG ?= verilog
+
+VERILOG_SOURCES += $(PWD)/my_design.sv
+# use VHDL_SOURCES for VHDL files
+
+# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
+TOPLEVEL = my_design
+
+# MODULE is the basename of the Python test file
+MODULE = test_my_design
+
+# include cocotb's make rules to take care of the simulator setup
+include $(shell cocotb-config --makefiles)/Makefile.sim
+