diff options
author | Jon Nordby <jononor@gmail.com> | 2025-04-26 18:02:35 +0200 |
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committer | Jon Nordby <jononor@gmail.com> | 2025-04-26 21:33:29 +0200 |
commit | ea5c8903b101708b49c2789ebc7d6e5f9453f119 (patch) | |
tree | 7b394710d31c39130954864705a1cfb48d05105b /cocotb_try/test_my_design.py | |
parent | 1c8497fa17f4c11e997641030d2e9c0f12e1b0bb (diff) |
cocotb: Try to run quickstart
Passes both using SIM=verilator and SIM=icarus
Diffstat (limited to 'cocotb_try/test_my_design.py')
-rw-r--r-- | cocotb_try/test_my_design.py | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/cocotb_try/test_my_design.py b/cocotb_try/test_my_design.py new file mode 100644 index 0000000..5136e31 --- /dev/null +++ b/cocotb_try/test_my_design.py @@ -0,0 +1,29 @@ + +# https://docs.cocotb.org/en/stable/quickstart.html +# test_my_design.py (extended) + +import cocotb +from cocotb.triggers import FallingEdge, Timer + + +async def generate_clock(dut): + """Generate clock pulses.""" + + for cycle in range(10): + dut.clk.value = 0 + await Timer(1, units="ns") + dut.clk.value = 1 + await Timer(1, units="ns") + + +@cocotb.test() +async def my_second_test(dut): + """Try accessing the design.""" + + await cocotb.start(generate_clock(dut)) # run the clock "in the background" + + await Timer(5, units="ns") # wait a bit + await FallingEdge(dut.clk) # wait for falling edge/"negedge" + + dut._log.info("my_signal_1 is %s", dut.my_signal_1.value) + assert dut.my_signal_2.value[0] == 0, "my_signal_2[0] is not 0!" |