diff options
| author | Jon Nordby <jononor@gmail.com> | 2025-04-26 18:13:37 +0200 |
|---|---|---|
| committer | Jon Nordby <jononor@gmail.com> | 2025-04-26 21:33:29 +0200 |
| commit | b9d821cb5409a545431d7b34d8df0ad493c26a46 (patch) | |
| tree | 7e196adc6e8e1548c6643c5e4c25e4fc0259bfd3 /cocotb_try/Makefile | |
| parent | b2b664b2596b48048ba97c5b43f3f29345c6bdb3 (diff) | |
cocotb: Try to test a CIC filter
Diffstat (limited to 'cocotb_try/Makefile')
| -rw-r--r-- | cocotb_try/Makefile | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cocotb_try/Makefile b/cocotb_try/Makefile index 2d4fe2b..6612173 100644 --- a/cocotb_try/Makefile +++ b/cocotb_try/Makefile @@ -4,14 +4,14 @@ SIM ?= verilator TOPLEVEL_LANG ?= verilog -VERILOG_SOURCES += $(PWD)/my_design.v +VERILOG_SOURCES += $(PWD)/cic3_pdm.v # use VHDL_SOURCES for VHDL files # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file -TOPLEVEL = my_design +TOPLEVEL = cic3_pdm # MODULE is the basename of the Python test file -MODULE = test_my_design +MODULE = test_cic # include cocotb's make rules to take care of the simulator setup include $(shell cocotb-config --makefiles)/Makefile.sim |