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| author | Martin Stensgård <mastensg@mastensg.net> | 2025-04-15 17:12:35 +0200 |
|---|---|---|
| committer | Martin Stensgård <mastensg@mastensg.net> | 2025-04-15 17:12:35 +0200 |
| commit | 9f053ec842668194a90717e2f8243e7f6b183bd7 (patch) | |
| tree | 8919cc972d9e54b349461a024bf5eaf9aa5fe153 /README | |
| parent | e73d5104384baf526cf905c729d8efe063bb60a6 (diff) | |
README: add references
Diffstat (limited to 'README')
| -rw-r--r-- | README | 13 |
1 files changed, 9 insertions, 4 deletions
@@ -4,10 +4,6 @@ Gate Array Learn make doas make load -Pulse Density Modulation - https://en.wikipedia.org/wiki/Pulse-code_modulation - https://curiouser.cheshireeng.com/2015/01/21/pdm-in-attiny85-source-code/ - Raspberry Pi UART Enable serial communication in raspi-config. @@ -18,3 +14,12 @@ UART pv /dev/ttyUSB1 > pcm.raw hexdump -ve '1/1 "%u\n"' pcm.raw > pcm.txt play -r 48k -e unsigned-integer -b 8 -c 1 pcm.raw + +References + Pulse Density Modulation + https://curiouser.cheshireeng.com/2015/01/21/pdm-in-attiny85-source-code/ + https://en.wikipedia.org/wiki/Pulse-code_modulation + https://tomverbeure.github.io/2020/10/04/PDM-Microphones-and-Sigma-Delta-Conversion.html + https://tomverbeure.github.io/2020/12/20/Design-of-a-Multi-Stage-PDM-to-PCM-Decimation-Pipeline.html + Verilog by Example (Blaine C. Raedler 2021) + http://readler.com/books2.html |