uart_benchmark: transmit U at 12 MBd

4 files changed, 134 insertions, 0 deletions

diff --git a/uart_benchmark/Makefile b/uart_benchmark/Makefile
new file mode 100644
index 0000000..1afafb7
--- /dev/null
+++ b/uart_benchmark/Makefile
@@ -0,0 +1,23 @@
+TOP = top
+
+all: check top.bin
+
+check:
+	verilator --lint-only --top $(TOP) top.v
+
+clean:
+	rm -f top.asc top.bin top.json
+
+load: all
+	iceprog top.bin
+
+.PHONY: all check clean load
+
+top.asc: top.json top.pcf
+	nextpnr-ice40 --hx1k --package tq144 --json top.json --pcf top.pcf --asc top.asc --top $(TOP)
+
+top.bin: top.asc
+	icepack top.asc top.bin
+
+top.json: top.v
+	yosys -q -p "synth_ice40 -json top.json -top $(TOP)" top.v
diff --git a/uart_benchmark/README b/uart_benchmark/README
new file mode 100644
index 0000000..9f24d6f
--- /dev/null
+++ b/uart_benchmark/README
@@ -0,0 +1,3 @@
+12 MHz clk  =>  12 MBd UART
+
+stty -F /dev/ttyUSB1 12000000 raw cs8
diff --git a/uart_benchmark/top.pcf b/uart_benchmark/top.pcf
new file mode 100644
index 0000000..b5ce785
--- /dev/null
+++ b/uart_benchmark/top.pcf
@@ -0,0 +1,28 @@
+set_io ftdi_tx	8
+set_io ftdi_rx	9
+
+set_io clk	21
+
+set_io p44	44
+set_io p45	45
+set_io p47	47
+set_io p48	48
+set_io p56	56
+set_io p60	60
+set_io p61	61
+set_io p62	62
+
+set_io p112	112
+set_io p113	113
+set_io p114	114
+set_io p115	115
+set_io p116	116
+set_io p117	117
+set_io p118	118
+set_io p119	119
+
+set_io D5	95
+set_io D1	96
+set_io D2	97
+set_io D3	98
+set_io D4	99
diff --git a/uart_benchmark/top.v b/uart_benchmark/top.v
new file mode 100644
index 0000000..e58fd97
--- /dev/null
+++ b/uart_benchmark/top.v
@@ -0,0 +1,80 @@
+module top(
+	input	clk,
+	output	ftdi_tx
+);
+	wire		clk_uart;
+	reg [7:0]	char = 8'h55;
+	reg		uart_go = 0;
+	wire		uart_ready;
+	uart_tx		uart_tx_1(clk_uart, char, uart_go, ftdi_tx, uart_ready);
+
+	always @(posedge clk) begin
+		uart_go <= uart_ready;
+	end
+
+	assign clk_uart = clk;
+endmodule
+
+module uart_tx(input clk, input [7:0] char, input go, output reg tx, output reg ready);
+	parameter s_ready =  0;
+	parameter s_start =  1;
+	parameter s_data0 =  2;
+	parameter s_data1 =  3;
+	parameter s_data2 =  4;
+	parameter s_data3 =  5;
+	parameter s_data4 =  6;
+	parameter s_data5 =  7;
+	parameter s_data6 =  8;
+	parameter s_data7 =  9;
+	parameter s_stop1 = 10;
+	parameter s_stop2 = 11;
+	parameter s_stop3 = 12;
+	parameter s_stop4 = 13;
+
+	reg [3:0]	state = s_ready;
+	reg [7:0]	data = 8'h41;
+
+	always @(posedge clk) begin
+		ready <= state == s_ready;
+		case (state)
+			s_ready: begin
+				if (go) begin
+					data <= char;
+					state <= s_start;
+				end
+			end
+			s_start:	state <= s_data0;
+			s_data0:	state <= s_data1;
+			s_data1:	state <= s_data2;
+			s_data2:	state <= s_data3;
+			s_data3:	state <= s_data4;
+			s_data4:	state <= s_data5;
+			s_data5:	state <= s_data6;
+			s_data6:	state <= s_data7;
+			s_data7:	state <= s_stop1;
+			s_stop1:	state <= s_stop2;
+			s_stop2:	state <= s_stop3;
+			s_stop3:	state <= s_stop4;
+			s_stop4: begin
+				if (!go)
+					state <= s_ready;
+			end
+		endcase
+		case (state)
+			s_ready:	tx <= 1;
+			s_start:	tx <= 0;
+			s_data0:	tx <= data[0];
+			s_data1:	tx <= data[1];
+			s_data2:	tx <= data[2];
+			s_data3:	tx <= data[3];
+			s_data4:	tx <= data[4];
+			s_data5:	tx <= data[5];
+			s_data6:	tx <= data[6];
+			s_data7:	tx <= data[7];
+			s_stop1:	tx <= 1;
+			s_stop2:	tx <= 1;
+			s_stop3:	tx <= 1;
+			s_stop4:	tx <= 1;
+		endcase
+	end
+endmodule