diff options
| author | Martin Stensgård <mastensg@mastensg.net> | 2026-03-14 21:08:19 +0100 |
|---|---|---|
| committer | Martin Stensgård <mastensg@mastensg.net> | 2026-03-14 21:08:19 +0100 |
| commit | 370d22c7fb00e5d2af2e164d415ad3375d6b3486 (patch) | |
| tree | 9e186cc2fe4dd9fa1519d7cd51143d732268ad83 /pcb/dickerpitter.kicad_pro | |
| parent | eb623f387a1ea17bf5acda74d56aee34d2c322a7 (diff) | |
pcie
Diffstat (limited to 'pcb/dickerpitter.kicad_pro')
| -rw-r--r-- | pcb/dickerpitter.kicad_pro | 63 |
1 files changed, 54 insertions, 9 deletions
diff --git a/pcb/dickerpitter.kicad_pro b/pcb/dickerpitter.kicad_pro index 9ee1890..93b06e5 100644 --- a/pcb/dickerpitter.kicad_pro +++ b/pcb/dickerpitter.kicad_pro @@ -187,7 +187,9 @@ } ], "track_widths": [ - 0.0 + 0.0, + 0.127, + 0.254 ], "tuning_pattern_settings": { "diff_pair_defaults": { @@ -471,21 +473,35 @@ "classes": [ { "bus_width": 12, - "clearance": 0.2, - "diff_pair_gap": 0.25, + "clearance": 0.11176, + "diff_pair_gap": 0.127, "diff_pair_via_gap": 0.25, - "diff_pair_width": 0.2, + "diff_pair_width": 0.127, "line_style": 0, - "microvia_diameter": 0.3, - "microvia_drill": 0.1, + "microvia_diameter": 0.45, + "microvia_drill": 0.3, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", "priority": 2147483647, "schematic_color": "rgba(0, 0, 0, 0.000)", - "track_width": 0.2, - "via_diameter": 0.6, + "track_width": 0.127, + "via_diameter": 0.45, "via_drill": 0.3, "wire_width": 6 + }, + { + "clearance": 0.127, + "diff_pair_gap": 0.127, + "diff_pair_width": 0.127, + "microvia_diameter": 0.45, + "microvia_drill": 0.3, + "name": "PCIe", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 0, + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.127, + "via_diameter": 0.45, + "via_drill": 0.3 } ], "meta": { @@ -493,7 +509,36 @@ }, "net_colors": null, "netclass_assignments": null, - "netclass_patterns": [] + "netclass_patterns": [ + { + "netclass": "Default", + "pattern": "" + }, + { + "netclass": "PCIe", + "pattern": "/PCIE_RX_N" + }, + { + "netclass": "PCIe", + "pattern": "/PCIE_RX_P" + }, + { + "netclass": "PCIe", + "pattern": "/PCIE_TX_P" + }, + { + "netclass": "PCIe", + "pattern": "/PCIE_CLK_P" + }, + { + "netclass": "PCIe", + "pattern": "/PCIE_CLK_N" + }, + { + "netclass": "PCIe", + "pattern": "/PCIE_TX_N" + } + ] }, "pcbnew": { "last_paths": { |