From cb019a43f55e08aa4c12573270a32213c823e1cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Stensg=C3=A5rd?= Date: Fri, 2 May 2025 20:52:27 +0200 Subject: verilator_lib: wrap verilog module in c++ library in c++ executable --- verilator_lib/sim.cc | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 verilator_lib/sim.cc (limited to 'verilator_lib/sim.cc') diff --git a/verilator_lib/sim.cc b/verilator_lib/sim.cc new file mode 100644 index 0000000..3ca8f67 --- /dev/null +++ b/verilator_lib/sim.cc @@ -0,0 +1,36 @@ +#include +#include + +#include "Vmul.h" +#include "verilated.h" + +enum { MAX = 10000 }; + +int +sim(void) +{ + VerilatedContext *cp = new VerilatedContext; + + Vmul *top = new Vmul{cp}; + top->clk = 0; + + int numclks = 0; + for (int x = 0; x < MAX; ++x) { + for (int y = 0; y < MAX; ++y) { + top->x = x; + top->y = y; + top->clk = 1; + top->eval(); + + int p = top->p; + if (p != (uint32_t)(x * y)) + printf("%4d * %4d = %4d\n", x, y, p); + + top->clk = 0; + top->eval(); + ++numclks; + } + } + fprintf(stderr, "%d clock cycles\n", numclks); + return 0; +} -- cgit v1.2.3