From ea5c8903b101708b49c2789ebc7d6e5f9453f119 Mon Sep 17 00:00:00 2001
From: Jon Nordby <jononor@gmail.com>
Date: Sat, 26 Apr 2025 18:02:35 +0200
Subject: cocotb: Try to run quickstart

Passes both using SIM=verilator and SIM=icarus
---
 cocotb_try/Makefile | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 cocotb_try/Makefile

(limited to 'cocotb_try/Makefile')

diff --git a/cocotb_try/Makefile b/cocotb_try/Makefile
new file mode 100644
index 0000000..2648771
--- /dev/null
+++ b/cocotb_try/Makefile
@@ -0,0 +1,18 @@
+# Makefile
+
+# defaults
+SIM ?= verilator
+TOPLEVEL_LANG ?= verilog
+
+VERILOG_SOURCES += $(PWD)/my_design.sv
+# use VHDL_SOURCES for VHDL files
+
+# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
+TOPLEVEL = my_design
+
+# MODULE is the basename of the Python test file
+MODULE = test_my_design
+
+# include cocotb's make rules to take care of the simulator setup
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
-- 
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