From b2b664b2596b48048ba97c5b43f3f29345c6bdb3 Mon Sep 17 00:00:00 2001 From: Jon Nordby Date: Sat, 26 Apr 2025 18:09:02 +0200 Subject: cocotb: Switch to plain Verilog, from SystemVerilog --- cocotb_try/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cocotb_try/Makefile') diff --git a/cocotb_try/Makefile b/cocotb_try/Makefile index 2648771..2d4fe2b 100644 --- a/cocotb_try/Makefile +++ b/cocotb_try/Makefile @@ -4,7 +4,7 @@ SIM ?= verilator TOPLEVEL_LANG ?= verilog -VERILOG_SOURCES += $(PWD)/my_design.sv +VERILOG_SOURCES += $(PWD)/my_design.v # use VHDL_SOURCES for VHDL files # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file -- cgit v1.2.3