From ea5c8903b101708b49c2789ebc7d6e5f9453f119 Mon Sep 17 00:00:00 2001 From: Jon Nordby Date: Sat, 26 Apr 2025 18:02:35 +0200 Subject: cocotb: Try to run quickstart Passes both using SIM=verilator and SIM=icarus --- cocotb_try/.gitignore | 3 +++ cocotb_try/Makefile | 18 ++++++++++++++++++ cocotb_try/my_design.sv | 15 +++++++++++++++ cocotb_try/test_my_design.py | 29 +++++++++++++++++++++++++++++ 4 files changed, 65 insertions(+) create mode 100644 cocotb_try/.gitignore create mode 100644 cocotb_try/Makefile create mode 100644 cocotb_try/my_design.sv create mode 100644 cocotb_try/test_my_design.py diff --git a/cocotb_try/.gitignore b/cocotb_try/.gitignore new file mode 100644 index 0000000..f0e6e9d --- /dev/null +++ b/cocotb_try/.gitignore @@ -0,0 +1,3 @@ +sim_build/ +__pycache__/ +results.xml diff --git a/cocotb_try/Makefile b/cocotb_try/Makefile new file mode 100644 index 0000000..2648771 --- /dev/null +++ b/cocotb_try/Makefile @@ -0,0 +1,18 @@ +# Makefile + +# defaults +SIM ?= verilator +TOPLEVEL_LANG ?= verilog + +VERILOG_SOURCES += $(PWD)/my_design.sv +# use VHDL_SOURCES for VHDL files + +# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file +TOPLEVEL = my_design + +# MODULE is the basename of the Python test file +MODULE = test_my_design + +# include cocotb's make rules to take care of the simulator setup +include $(shell cocotb-config --makefiles)/Makefile.sim + diff --git a/cocotb_try/my_design.sv b/cocotb_try/my_design.sv new file mode 100644 index 0000000..458ac8e --- /dev/null +++ b/cocotb_try/my_design.sv @@ -0,0 +1,15 @@ +// This file is public domain, it can be freely copied without restrictions. +// SPDX-License-Identifier: CC0-1.0 + +module my_design(input logic clk); + + timeunit 1ns; + timeprecision 1ns; + + logic my_signal_1; + logic my_signal_2; + + assign my_signal_1 = 1'bx; + assign my_signal_2 = 0; + +endmodule diff --git a/cocotb_try/test_my_design.py b/cocotb_try/test_my_design.py new file mode 100644 index 0000000..5136e31 --- /dev/null +++ b/cocotb_try/test_my_design.py @@ -0,0 +1,29 @@ + +# https://docs.cocotb.org/en/stable/quickstart.html +# test_my_design.py (extended) + +import cocotb +from cocotb.triggers import FallingEdge, Timer + + +async def generate_clock(dut): + """Generate clock pulses.""" + + for cycle in range(10): + dut.clk.value = 0 + await Timer(1, units="ns") + dut.clk.value = 1 + await Timer(1, units="ns") + + +@cocotb.test() +async def my_second_test(dut): + """Try accessing the design.""" + + await cocotb.start(generate_clock(dut)) # run the clock "in the background" + + await Timer(5, units="ns") # wait a bit + await FallingEdge(dut.clk) # wait for falling edge/"negedge" + + dut._log.info("my_signal_1 is %s", dut.my_signal_1.value) + assert dut.my_signal_2.value[0] == 0, "my_signal_2[0] is not 0!" -- cgit v1.2.3