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Commit message (Collapse)AuthorAge
* pdm: Try switch to 2 stage CICJon Nordby2025-08-08
| | | | Still seeing odd spikes on output
* pdm: Try more HPF fixesJon Nordby2025-08-08
| | | | Still not right. Seeing periodic steps on output, that settle to 0, repeatedly
* pdm: Try add high pass filter for DC blocking/removalJon Nordby2025-08-08
| | | | Does not work right...
* cic3_pdm: Silence a warning from VerilatorJon Nordby2025-05-14
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* bindings: Actually build cic3_pdm codeJon Nordby2025-05-14
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* Remove unused pdm_outJon Nordby2025-05-02
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* cocotb: Have two tests, share coreJon Nordby2025-05-02
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* cocotb: Specify some argumentsJon Nordby2025-05-02
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* cocotb: Test and fix 1khz sineJon Nordby2025-05-02
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* cocotb: Run multiple PCM samplesJon Nordby2025-04-26
| | | | 1000 samples is quite slow, takes many seconds
* cocotb: Try to test a CIC filterJon Nordby2025-04-26
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* cocotb: Switch to plain Verilog, from SystemVerilogJon Nordby2025-04-26
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* cocotb: Try to run quickstartJon Nordby2025-04-26
Passes both using SIM=verilator and SIM=icarus
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-19 02:40:01 +0000