2 files changed, 30 insertions, 9 deletions
diff --git a/cocotb_try/cic3_pdm.v b/cocotb_try/cic3_pdm.v
index f572d64..1c8ba25 100644
--- a/cocotb_try/cic3_pdm.v
+++ b/cocotb_try/cic3_pdm.v
@@ -6,7 +6,9 @@ module cic3_pdm (
     input  wire        rst,        // active-high synchronous reset
     input  wire        pdm_in,     // 1-bit PDM data input
     output wire signed [15:0] pcm_out, // Decimated PCM output
-    output wire        pcm_valid   // High when pcm_out is valid
+    output wire        pcm_valid,   // High when pcm_out is valid       
+    output reg        pdm_out
+
 );
     parameter DECIMATION = 64; // Decimation factor
 
@@ -46,7 +48,7 @@ module cic3_pdm (
     // Comb stage (runs every DECIMATION clocks)
     always @(posedge clk) begin
         pcm_valid_r <= 0;
-        if (decim_counter == DECIMATION[5:0] - 1) begin
+        if (decim_counter == 63) begin
             comb_0 <= integrator_2 - delay_0;
             delay_0 <= integrator_2;
 
@@ -57,6 +59,7 @@ module cic3_pdm (
             delay_2 <= comb_1;
 
             // Bit-shift down to get 16-bit output (tune shift based on DECIMATION and stage count)
+            pdm_out <= pdm_in;
             pcm_out_r <= comb_2[31:16]; 
             pcm_valid_r <= 1;
         end
diff --git a/cocotb_try/test_cic.py b/cocotb_try/test_cic.py
index 3a4e385..19a17f9 100644
--- a/cocotb_try/test_cic.py
+++ b/cocotb_try/test_cic.py
@@ -3,7 +3,8 @@
 # test_my_design.py (extended)
 
 import cocotb
-from cocotb.triggers import FallingEdge, Timer
+from cocotb.triggers import FallingEdge, RisingEdge, Timer, with_timeout
+from cocotb.clock import Clock
 
 
 async def generate_clock(dut):
@@ -15,18 +16,35 @@ async def generate_clock(dut):
         dut.clk.value = 1
         await Timer(1, units="ns")
 
+async def drive_waveform(dut, waveform):
+    for a_val in waveform:
+        dut.pdm_in.value = a_val
+        await RisingEdge(dut.clk)
+
 
 @cocotb.test()
 async def my_second_test(dut):
-    """Try accessing the design."""
+    """Try running with PDM input"""
+
+    #dut.rst.value = 1
+    #await RisingEdge(dut.clk)
+    #dut.rst.value = 0
 
-    await cocotb.start(generate_clock(dut))  # run the clock "in the background"
+    pcm_samples = 10
+    decimation = 64
+    pdm_data = [0, 0, 1] * (pcm_samples*decimation)
 
-    await Timer(5, units="ns")  # wait a bit
-    await FallingEdge(dut.clk)  # wait for falling edge/"negedge"
+    cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+    cocotb.start_soon(drive_waveform(dut, pdm_data))
 
-    dut._log.info("my_signal_1 is %s", dut.my_signal_1.value)
-    assert dut.my_signal_2.value[0] == 0, "my_signal_2[0] is not 0!"
+    # wait for the PCM output
+    for _ in range(pcm_samples):
+        await with_timeout(RisingEdge(dut.pcm_valid), 100000, 'ns')
+        dut._log.info("PCM is %s", dut.pcm_out.value)
 
+    #dut._log.info("pdm_out is %s", dut.pdm_out.value)
+    #assert dut.pdm_out.value == 1
 
+    dut._log.info("my_signal_1 is %s", dut.pcm_out.value)
+    assert dut.pcm_out.value == 1212