diff options
| -rw-r--r-- | verilator_add/.gitignore | 1 | ||||
| -rw-r--r-- | verilator_add/Makefile | 12 | ||||
| -rw-r--r-- | verilator_add/add.v | 10 | ||||
| -rw-r--r-- | verilator_add/sim_main.cc | 36 |
4 files changed, 59 insertions, 0 deletions
diff --git a/verilator_add/.gitignore b/verilator_add/.gitignore new file mode 100644 index 0000000..d38e9f1 --- /dev/null +++ b/verilator_add/.gitignore @@ -0,0 +1 @@ +/obj_dir diff --git a/verilator_add/Makefile b/verilator_add/Makefile new file mode 100644 index 0000000..86cdb8c --- /dev/null +++ b/verilator_add/Makefile @@ -0,0 +1,12 @@ +all: obj_dir/Vadd + +check: all + obj_dir/Vadd + +clean: + rm -fr obj_dir + +.PHONY: all check clean + +obj_dir/Vadd: add.v sim_main.cc + verilator --cc --exe --build -j 0 -Wall sim_main.cc add.v diff --git a/verilator_add/add.v b/verilator_add/add.v new file mode 100644 index 0000000..240c97e --- /dev/null +++ b/verilator_add/add.v @@ -0,0 +1,10 @@ +module add( + input clk, + input [7:0] x, + input [7:0] y, + output reg [7:0] s +); + always @(posedge clk) begin + s <= x + y; + end +endmodule diff --git a/verilator_add/sim_main.cc b/verilator_add/sim_main.cc new file mode 100644 index 0000000..6059d63 --- /dev/null +++ b/verilator_add/sim_main.cc @@ -0,0 +1,36 @@ +#include <cstdint> +#include <cstdio> + +#include "Vadd.h" +#include "verilated.h" + +enum { MAX = 10000 }; + +int +main(int argc, char **argv) +{ + VerilatedContext *cp = new VerilatedContext; + cp->commandArgs(argc, argv); + + Vadd *top = new Vadd{cp}; + top->clk = 0; + + int numclks = 0; + for (int x = 0; x < MAX; ++x) { + for (int y = 0; y < MAX; ++y) { + top->x = x; + top->y = y; + top->clk = 1; + top->eval(); + + int s = top->s; + if (s != (uint8_t)(x + y)) + printf("%4d + %4d = %4d\n", x, y, s); + + top->clk = 0; + top->eval(); + ++numclks; + } + } + fprintf(stderr, "%d clock cycles\n", numclks); +} |