diff options
| -rw-r--r-- | .gitignore | 5 | ||||
| -rw-r--r-- | Makefile | 23 | ||||
| -rw-r--r-- | README | 4 | ||||
| -rw-r--r-- | top.pcf | 28 | ||||
| -rw-r--r-- | top.v | 110 |
5 files changed, 170 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..0ba0593 --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +top.asc +top.bin +top.blif +top.ex +top.json diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..1afafb7 --- /dev/null +++ b/Makefile @@ -0,0 +1,23 @@ +TOP = top + +all: check top.bin + +check: + verilator --lint-only --top $(TOP) top.v + +clean: + rm -f top.asc top.bin top.json + +load: all + iceprog top.bin + +.PHONY: all check clean load + +top.asc: top.json top.pcf + nextpnr-ice40 --hx1k --package tq144 --json top.json --pcf top.pcf --asc top.asc --top $(TOP) + +top.bin: top.asc + icepack top.asc top.bin + +top.json: top.v + yosys -q -p "synth_ice40 -json top.json -top $(TOP)" top.v @@ -1 +1,5 @@ Gate Array Learn + + apt install yosys fpga-icestorm nextpnr-ice40 + make + doas make load @@ -0,0 +1,28 @@ +set_io ftdi_tx 8 +set_io ftdi_rx 9 + +set_io clk 21 + +set_io p44 44 +set_io p45 45 +set_io p47 47 +set_io p48 48 +set_io p56 56 +set_io p60 60 +set_io p61 61 +set_io p62 62 + +set_io p112 112 +set_io p113 113 +set_io p114 114 +set_io p115 115 +set_io p116 116 +set_io p117 117 +set_io p118 118 +set_io p119 119 + +set_io D5 95 +set_io D1 96 +set_io D2 97 +set_io D3 98 +set_io D4 99 @@ -0,0 +1,110 @@ +module top( + input clk, + input ftdi_rx, + output D1, + output D2, + output D3, + output D4, + output D5, + output ftdi_tx, + output p44, + input p45 +); + wire clk_uart; + + reg [7:0] char = 8'h6f; + reg go = 0; + + rot rot_1(ftdi_rx, {D1, D2, D3, D4}); + clk_div_uart clk_div_uart_1(clk, clk_uart); + uart_tx uart_tx_1(clk_uart, char, go, ftdi_tx, p44); + + reg [23:0] t = 0; + always @(posedge clk) begin + t <= t<12000000 ? t+1 : 0; + go = t<9000000; + end + + assign D5 = go; + + //assign p44 = clk_uart; + //assign p44 = ftdi_tx; +endmodule + +module rot(input clk, output [3:0] d); + reg [3:0] r = 4'b1000; + always @(posedge clk) r <= {r[0], r[3:1]}; + assign d = r; +endmodule + +module clk_div_uart(input clk, output reg clk_uart); + reg [10:0] t = 0; + always @(posedge clk) begin + t <= t<1250-1 ? t+1 : 0; + clk_uart <= t<625; + end +endmodule + +module uart_tx(input clk, input [7:0] char, input go, output reg tx, output reg ready); + parameter s_ready = 0; + parameter s_start = 1; + parameter s_data0 = 2; + parameter s_data1 = 3; + parameter s_data2 = 4; + parameter s_data3 = 5; + parameter s_data4 = 6; + parameter s_data5 = 7; + parameter s_data6 = 8; + parameter s_data7 = 9; + parameter s_stop1 = 10; + parameter s_stop2 = 11; + parameter s_stop3 = 12; + parameter s_stop4 = 13; + + reg [3:0] state = s_ready; + reg [7:0] data = 8'h41; + + always @(posedge clk) begin + ready <= state == s_ready; + case (state) + s_ready: begin + if (go) begin + data <= char; + state <= s_start; + end + end + s_start: state <= s_data0; + s_data0: state <= s_data1; + s_data1: state <= s_data2; + s_data2: state <= s_data3; + s_data3: state <= s_data4; + s_data4: state <= s_data5; + s_data5: state <= s_data6; + s_data6: state <= s_data7; + s_data7: state <= s_stop1; + s_stop1: state <= s_stop2; + s_stop2: state <= s_stop3; + s_stop3: state <= s_stop4; + s_stop4: begin + if (!go) + state <= s_ready; + end + endcase + case (state) + s_ready: tx <= 1; + s_start: tx <= 0; + s_data0: tx <= data[0]; + s_data1: tx <= data[1]; + s_data2: tx <= data[2]; + s_data3: tx <= data[3]; + s_data4: tx <= data[4]; + s_data5: tx <= data[5]; + s_data6: tx <= data[6]; + s_data7: tx <= data[7]; + s_stop1: tx <= 1; + s_stop2: tx <= 1; + s_stop3: tx <= 1; + s_stop4: tx <= 1; + endcase + end +endmodule |