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<title>galearn/cocotb_try/Makefile, branch master</title>
<subtitle>Gate Array Learn
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<entry>
<title>cocotb: Specify some arguments</title>
<updated>2025-05-02T19:00:12+00:00</updated>
<author>
<name>Jon Nordby</name>
<email>jononor@gmail.com</email>
</author>
<published>2025-04-27T14:25:34+00:00</published>
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<entry>
<title>cocotb: Try to test a CIC filter</title>
<updated>2025-04-26T19:33:29+00:00</updated>
<author>
<name>Jon Nordby</name>
<email>jononor@gmail.com</email>
</author>
<published>2025-04-26T16:13:37+00:00</published>
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<entry>
<title>cocotb: Switch to plain Verilog, from SystemVerilog</title>
<updated>2025-04-26T19:33:29+00:00</updated>
<author>
<name>Jon Nordby</name>
<email>jononor@gmail.com</email>
</author>
<published>2025-04-26T16:09:02+00:00</published>
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<entry>
<title>cocotb: Try to run quickstart</title>
<updated>2025-04-26T19:33:29+00:00</updated>
<author>
<name>Jon Nordby</name>
<email>jononor@gmail.com</email>
</author>
<published>2025-04-26T16:02:35+00:00</published>
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Passes both using SIM=verilator and SIM=icarus
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Passes both using SIM=verilator and SIM=icarus
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